--------------------------------------------------------------------------------
-- Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  /    Vendor: Xilinx
-- \   \   \/     Version: L.33
--  \   \         Application: netgen
--  /   /         Filename: schema_timesim.vhd
-- /___/   /\     Timestamp: Mon Jun 14 22:55:59 2010
-- \   \  /  \ 
--  \___\/\___\
--             
-- Command	: -intstyle ise -s 5 -pcf schema.pcf -rpw 100 -tpw 0 -ar Structure -tm schema -insert_pp_buffers false -w -dir netgen/par -ofmt vhdl -sim schema.ncd schema_timesim.vhd 
-- Device	: 3s100ecp132-5 (PRODUCTION 1.27 2009-03-03)
-- Input file	: schema.ncd
-- Output file	: C:\xilinks\Pokus2\netgen\par\schema_timesim.vhd
-- # of Entities	: 1
-- Design Name	: schema
-- Xilinx	: C:\Xilinx\11.1\ISE
--             
-- Purpose:    
--     This VHDL netlist is a verification model and uses simulation 
--     primitives which may not represent the true implementation of the 
--     device, however the netlist is functionally correct and should not 
--     be modified. This file cannot be synthesized and should only be used 
--     with supported simulation tools.
--             
-- Reference:  
--     Development System Reference Guide, Chapter 23
--     Synthesis and Simulation Design Guide, Chapter 6
--             
--------------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity schema is
  port (
    ca : out STD_LOGIC; 
    cb : out STD_LOGIC; 
    cc : out STD_LOGIC; 
    cd : out STD_LOGIC; 
    ce : out STD_LOGIC; 
    cf : out STD_LOGIC; 
    cg : out STD_LOGIC; 
    dp : out STD_LOGIC; 
    sw_0 : in STD_LOGIC := 'X'; 
    sw_1 : in STD_LOGIC := 'X'; 
    ld_0 : out STD_LOGIC; 
    sw_2 : in STD_LOGIC := 'X'; 
    ld_1 : out STD_LOGIC; 
    sw_3 : in STD_LOGIC := 'X'; 
    ld_2 : out STD_LOGIC; 
    ld_6 : out STD_LOGIC; 
    ld_7 : out STD_LOGIC; 
    clk_1Hz : in STD_LOGIC := 'X'; 
    an_0 : out STD_LOGIC; 
    an_1 : out STD_LOGIC; 
    an_2 : out STD_LOGIC; 
    an_3 : out STD_LOGIC; 
    btn_0 : in STD_LOGIC := 'X'; 
    btn_1 : in STD_LOGIC := 'X' 
  );
end schema;

architecture Structure of schema is
  signal clk_1Hz_IBUF1 : STD_LOGIC; 
  signal btn_0_IBUF_130 : STD_LOGIC; 
  signal ld_0_OBUF_131 : STD_LOGIC; 
  signal ld_1_OBUF_132 : STD_LOGIC; 
  signal ld_2_OBUF_133 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal clk_1Hz_IBUF_142 : STD_LOGIC; 
  signal ce_O : STD_LOGIC; 
  signal cf_O : STD_LOGIC; 
  signal cg_O : STD_LOGIC; 
  signal clk_1Hz_IBUF_BUFG_S_INVNOT : STD_LOGIC; 
  signal clk_1Hz_IBUF_BUFG_I0_INV : STD_LOGIC; 
  signal ld_0_OBUF_DXMUX_356 : STD_LOGIC; 
  signal XLXN_31 : STD_LOGIC; 
  signal ld_0_OBUF_DYMUX_345 : STD_LOGIC; 
  signal XLXN_29 : STD_LOGIC; 
  signal ld_0_OBUF_CLKINV_337 : STD_LOGIC; 
  signal XLXI_36_XLXN_82 : STD_LOGIC; 
  signal ld_1_OBUF_DYMUX_378 : STD_LOGIC; 
  signal XLXN_30 : STD_LOGIC; 
  signal ld_1_OBUF_CLKINV_370 : STD_LOGIC; 
  signal ca_OBUF_411 : STD_LOGIC; 
  signal cd_OBUF_403 : STD_LOGIC; 
  signal cb_OBUF_435 : STD_LOGIC; 
  signal ce_OBUF_427 : STD_LOGIC; 
  signal cg_OBUF_459 : STD_LOGIC; 
  signal cf_OBUF_451 : STD_LOGIC; 
  signal clk_1Hz_INBUF : STD_LOGIC; 
  signal dp_O : STD_LOGIC; 
  signal sw_0_INBUF : STD_LOGIC; 
  signal sw_1_INBUF : STD_LOGIC; 
  signal sw_2_INBUF : STD_LOGIC; 
  signal sw_3_INBUF : STD_LOGIC; 
  signal an_0_O : STD_LOGIC; 
  signal an_1_O : STD_LOGIC; 
  signal an_2_O : STD_LOGIC; 
  signal btn_0_INBUF : STD_LOGIC; 
  signal an_3_O : STD_LOGIC; 
  signal btn_1_INBUF : STD_LOGIC; 
  signal ld_0_O : STD_LOGIC; 
  signal ld_1_O : STD_LOGIC; 
  signal ld_2_O : STD_LOGIC; 
  signal ca_O : STD_LOGIC; 
  signal ld_6_O : STD_LOGIC; 
  signal cb_O : STD_LOGIC; 
  signal ld_7_O : STD_LOGIC; 
  signal cc_O : STD_LOGIC; 
  signal cd_O : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
begin
  ce_OBUF : X_OBUF
    generic map(
      LOC => "PAD56"
    )
    port map (
      I => ce_O,
      O => ce
    );
  cf_OBUF : X_OBUF
    generic map(
      LOC => "PAD49"
    )
    port map (
      I => cf_O,
      O => cf
    );
  cg_OBUF : X_OBUF
    generic map(
      LOC => "PAD52"
    )
    port map (
      I => cg_O,
      O => cg
    );
  clk_1Hz_IBUF_BUFG : X_BUFGMUX
    generic map(
      LOC => "BUFGMUX_X2Y10"
    )
    port map (
      I0 => clk_1Hz_IBUF_BUFG_I0_INV,
      I1 => GND,
      S => clk_1Hz_IBUF_BUFG_S_INVNOT,
      O => clk_1Hz_IBUF_142
    );
  clk_1Hz_IBUF_BUFG_SINV : X_INV
    generic map(
      LOC => "BUFGMUX_X2Y10",
      PATHPULSE => 694 ps
    )
    port map (
      I => GLOBAL_LOGIC1,
      O => clk_1Hz_IBUF_BUFG_S_INVNOT
    );
  clk_1Hz_IBUF_BUFG_I0_USED : X_BUF
    generic map(
      LOC => "BUFGMUX_X2Y10",
      PATHPULSE => 694 ps
    )
    port map (
      I => clk_1Hz_IBUF1,
      O => clk_1Hz_IBUF_BUFG_I0_INV
    );
  ld_0_OBUF_DXMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y18",
      PATHPULSE => 694 ps
    )
    port map (
      I => XLXN_31,
      O => ld_0_OBUF_DXMUX_356
    );
  ld_0_OBUF_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X27Y18",
      PATHPULSE => 694 ps
    )
    port map (
      I => XLXN_29,
      O => ld_0_OBUF_DYMUX_345
    );
  ld_0_OBUF_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X27Y18",
      PATHPULSE => 694 ps
    )
    port map (
      I => clk_1Hz_IBUF_142,
      O => ld_0_OBUF_CLKINV_337
    );
  XLXI_43 : X_LUT4
    generic map(
      INIT => X"1032",
      LOC => "SLICE_X27Y18"
    )
    port map (
      ADR0 => ld_2_OBUF_133,
      ADR1 => btn_0_IBUF_130,
      ADR2 => ld_1_OBUF_132,
      ADR3 => ld_0_OBUF_131,
      O => XLXN_29
    );
  ld_1_OBUF_DYMUX : X_BUF
    generic map(
      LOC => "SLICE_X28Y18",
      PATHPULSE => 694 ps
    )
    port map (
      I => XLXN_30,
      O => ld_1_OBUF_DYMUX_378
    );
  ld_1_OBUF_CLKINV : X_BUF
    generic map(
      LOC => "SLICE_X28Y18",
      PATHPULSE => 694 ps
    )
    port map (
      I => clk_1Hz_IBUF_142,
      O => ld_1_OBUF_CLKINV_370
    );
  XLXI_44 : X_LUT4
    generic map(
      INIT => X"0454",
      LOC => "SLICE_X28Y18"
    )
    port map (
      ADR0 => btn_0_IBUF_130,
      ADR1 => ld_1_OBUF_132,
      ADR2 => ld_0_OBUF_131,
      ADR3 => ld_2_OBUF_133,
      O => XLXN_30
    );
  XLXI_36_XLXI_121 : X_LUT4
    generic map(
      INIT => X"9944",
      LOC => "SLICE_X29Y8"
    )
    port map (
      ADR0 => ld_1_OBUF_132,
      ADR1 => ld_2_OBUF_133,
      ADR2 => VCC,
      ADR3 => ld_0_OBUF_131,
      O => cd_OBUF_403
    );
  XLXI_36_XLXI_122 : X_LUT4
    generic map(
      INIT => X"DCDC",
      LOC => "SLICE_X30Y12"
    )
    port map (
      ADR0 => ld_1_OBUF_132,
      ADR1 => ld_0_OBUF_131,
      ADR2 => ld_2_OBUF_133,
      ADR3 => VCC,
      O => ce_OBUF_427
    );
  XLXI_36_XLXI_123 : X_LUT4
    generic map(
      INIT => X"F330",
      LOC => "SLICE_X31Y9"
    )
    port map (
      ADR0 => VCC,
      ADR1 => ld_2_OBUF_133,
      ADR2 => ld_0_OBUF_131,
      ADR3 => ld_1_OBUF_132,
      O => cf_OBUF_451
    );
  clk_1Hz_IBUF : X_BUF
    generic map(
      LOC => "IPAD12",
      PATHPULSE => 694 ps
    )
    port map (
      I => clk_1Hz,
      O => clk_1Hz_INBUF
    );
  clk_1Hz_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD12",
      PATHPULSE => 694 ps
    )
    port map (
      I => clk_1Hz_INBUF,
      O => clk_1Hz_IBUF1
    );
  dp_OBUF : X_OBUF
    generic map(
      LOC => "PAD54"
    )
    port map (
      I => dp_O,
      O => dp
    );
  sw_0_IBUF : X_BUF
    generic map(
      LOC => "IPAD60",
      PATHPULSE => 694 ps
    )
    port map (
      I => sw_0,
      O => sw_0_INBUF
    );
  sw_1_IBUF : X_BUF
    generic map(
      LOC => "PAD83",
      PATHPULSE => 694 ps
    )
    port map (
      I => sw_1,
      O => sw_1_INBUF
    );
  sw_2_IBUF : X_BUF
    generic map(
      LOC => "IPAD86",
      PATHPULSE => 694 ps
    )
    port map (
      I => sw_2,
      O => sw_2_INBUF
    );
  sw_3_IBUF : X_BUF
    generic map(
      LOC => "IPAD3",
      PATHPULSE => 694 ps
    )
    port map (
      I => sw_3,
      O => sw_3_INBUF
    );
  an_0_OBUF : X_OBUF
    generic map(
      LOC => "PAD33"
    )
    port map (
      I => an_0_O,
      O => an_0
    );
  an_1_OBUF : X_OBUF
    generic map(
      LOC => "PAD44"
    )
    port map (
      I => an_1_O,
      O => an_1
    );
  an_2_OBUF : X_OBUF
    generic map(
      LOC => "PAD51"
    )
    port map (
      I => an_2_O,
      O => an_2
    );
  btn_0_IBUF : X_BUF
    generic map(
      LOC => "IPAD36",
      PATHPULSE => 694 ps
    )
    port map (
      I => btn_0,
      O => btn_0_INBUF
    );
  btn_0_IFF_IMUX : X_BUF
    generic map(
      LOC => "IPAD36",
      PATHPULSE => 694 ps
    )
    port map (
      I => btn_0_INBUF,
      O => btn_0_IBUF_130
    );
  an_3_OBUF : X_OBUF
    generic map(
      LOC => "PAD45"
    )
    port map (
      I => an_3_O,
      O => an_3
    );
  btn_1_IBUF : X_BUF
    generic map(
      LOC => "IPAD23",
      PATHPULSE => 694 ps
    )
    port map (
      I => btn_1,
      O => btn_1_INBUF
    );
  ld_0_OBUF : X_OBUF
    generic map(
      LOC => "PAD69"
    )
    port map (
      I => ld_0_O,
      O => ld_0
    );
  ld_1_OBUF : X_OBUF
    generic map(
      LOC => "PAD58"
    )
    port map (
      I => ld_1_O,
      O => ld_1
    );
  ld_2_OBUF : X_OBUF
    generic map(
      LOC => "PAD64"
    )
    port map (
      I => ld_2_O,
      O => ld_2
    );
  ca_OBUF : X_OBUF
    generic map(
      LOC => "PAD48"
    )
    port map (
      I => ca_O,
      O => ca
    );
  ld_6_OBUF : X_OBUF
    generic map(
      LOC => "PAD70"
    )
    port map (
      I => ld_6_O,
      O => ld_6
    );
  cb_OBUF : X_OBUF
    generic map(
      LOC => "PAD39"
    )
    port map (
      I => cb_O,
      O => cb
    );
  ld_7_OBUF : X_OBUF
    generic map(
      LOC => "PAD96"
    )
    port map (
      I => ld_7_O,
      O => ld_7
    );
  cc_OBUF : X_OBUF
    generic map(
      LOC => "PAD53"
    )
    port map (
      I => cc_O,
      O => cc
    );
  cd_OBUF : X_OBUF
    generic map(
      LOC => "PAD59"
    )
    port map (
      I => cd_O,
      O => cd
    );
  XLXI_36_XLXI_119 : X_LUT4
    generic map(
      INIT => X"6060",
      LOC => "SLICE_X30Y12"
    )
    port map (
      ADR0 => ld_1_OBUF_132,
      ADR1 => ld_0_OBUF_131,
      ADR2 => ld_2_OBUF_133,
      ADR3 => VCC,
      O => cb_OBUF_435
    );
  XLXI_36_XLXI_124 : X_LUT4
    generic map(
      INIT => X"C033",
      LOC => "SLICE_X31Y9"
    )
    port map (
      ADR0 => VCC,
      ADR1 => ld_2_OBUF_133,
      ADR2 => ld_0_OBUF_131,
      ADR3 => ld_1_OBUF_132,
      O => cg_OBUF_459
    );
  XLXI_21 : X_FF
    generic map(
      LOC => "SLICE_X27Y18",
      INIT => '0'
    )
    port map (
      I => ld_0_OBUF_DYMUX_345,
      CE => VCC,
      CLK => ld_0_OBUF_CLKINV_337,
      SET => GND,
      RST => GND,
      O => ld_2_OBUF_133
    );
  XLXI_45 : X_LUT4
    generic map(
      INIT => X"0023",
      LOC => "SLICE_X27Y18"
    )
    port map (
      ADR0 => ld_2_OBUF_133,
      ADR1 => btn_0_IBUF_130,
      ADR2 => ld_1_OBUF_132,
      ADR3 => ld_0_OBUF_131,
      O => XLXN_31
    );
  XLXI_23 : X_FF
    generic map(
      LOC => "SLICE_X27Y18",
      INIT => '0'
    )
    port map (
      I => ld_0_OBUF_DXMUX_356,
      CE => VCC,
      CLK => ld_0_OBUF_CLKINV_337,
      SET => GND,
      RST => GND,
      O => ld_0_OBUF_131
    );
  XLXI_22 : X_FF
    generic map(
      LOC => "SLICE_X28Y18",
      INIT => '0'
    )
    port map (
      I => ld_1_OBUF_DYMUX_378,
      CE => VCC,
      CLK => ld_1_OBUF_CLKINV_370,
      SET => GND,
      RST => GND,
      O => ld_1_OBUF_132
    );
  XLXI_36_XLXI_71 : X_LUT4
    generic map(
      INIT => X"000C",
      LOC => "SLICE_X28Y18"
    )
    port map (
      ADR0 => VCC,
      ADR1 => ld_1_OBUF_132,
      ADR2 => ld_0_OBUF_131,
      ADR3 => ld_2_OBUF_133,
      O => XLXI_36_XLXN_82
    );
  XLXI_36_XLXI_118 : X_LUT4
    generic map(
      INIT => X"1144",
      LOC => "SLICE_X29Y8"
    )
    port map (
      ADR0 => ld_1_OBUF_132,
      ADR1 => ld_2_OBUF_133,
      ADR2 => VCC,
      ADR3 => ld_0_OBUF_131,
      O => ca_OBUF_411
    );
  GLOBAL_LOGIC1_VCC : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  ce_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD56",
      PATHPULSE => 694 ps
    )
    port map (
      I => ce_OBUF_427,
      O => ce_O
    );
  cf_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD49",
      PATHPULSE => 694 ps
    )
    port map (
      I => cf_OBUF_451,
      O => cf_O
    );
  cg_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD52",
      PATHPULSE => 694 ps
    )
    port map (
      I => cg_OBUF_459,
      O => cg_O
    );
  dp_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD54",
      PATHPULSE => 694 ps
    )
    port map (
      I => btn_1_INBUF,
      O => dp_O
    );
  an_0_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD33",
      PATHPULSE => 694 ps
    )
    port map (
      I => sw_3_INBUF,
      O => an_0_O
    );
  an_1_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD44",
      PATHPULSE => 694 ps
    )
    port map (
      I => sw_2_INBUF,
      O => an_1_O
    );
  an_2_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD51",
      PATHPULSE => 694 ps
    )
    port map (
      I => sw_1_INBUF,
      O => an_2_O
    );
  an_3_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD45",
      PATHPULSE => 694 ps
    )
    port map (
      I => sw_0_INBUF,
      O => an_3_O
    );
  ld_0_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD69",
      PATHPULSE => 694 ps
    )
    port map (
      I => ld_0_OBUF_131,
      O => ld_0_O
    );
  ld_1_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD58",
      PATHPULSE => 694 ps
    )
    port map (
      I => ld_1_OBUF_132,
      O => ld_1_O
    );
  ld_2_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD64",
      PATHPULSE => 694 ps
    )
    port map (
      I => ld_2_OBUF_133,
      O => ld_2_O
    );
  ca_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD48",
      PATHPULSE => 694 ps
    )
    port map (
      I => ca_OBUF_411,
      O => ca_O
    );
  ld_6_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD70",
      PATHPULSE => 694 ps
    )
    port map (
      I => clk_1Hz_IBUF1,
      O => ld_6_O
    );
  cb_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD39",
      PATHPULSE => 694 ps
    )
    port map (
      I => cb_OBUF_435,
      O => cb_O
    );
  ld_7_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD96",
      PATHPULSE => 694 ps
    )
    port map (
      I => btn_0_IBUF_130,
      O => ld_7_O
    );
  cc_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD53",
      PATHPULSE => 694 ps
    )
    port map (
      I => XLXI_36_XLXN_82,
      O => cc_O
    );
  cd_OUTPUT_OFF_OMUX : X_BUF
    generic map(
      LOC => "PAD59",
      PATHPULSE => 694 ps
    )
    port map (
      I => cd_OBUF_403,
      O => cd_O
    );
  NlwBlock_schema_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlock_schema_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

